FPGA/HDLBits

Combine circuits A and B (Mt2015 q4)

장영현 2023. 6. 12. 15:49
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Problem Statement

aken from 2015 midterm question 4

See mt2015_q4a and mt2015_q4b for the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

module top_module (input x, input y, output z);
    wire z1,z2,z3,z4;
    mt2015_q4a IA1(
        .x(x),
        .y(y),
        .z(z1));
    mt2015_q4a IA2(
        .x(x),
        .y(y),
        .z(z2));
    mt2015_q4b IB1(
        .x(x),
        .y(y),
        .z(z3));
    mt2015_q4b IB2(
        .x(x),
        .y(y),
        .z(z4));
    assign z = (z1 | z3) ^ (z2 & z4);
endmodule

module mt2015_q4a (input  x, input y, output z);
    assign z = (x^y) & x;
endmodule

module mt2015_q4b (input x, input y, output z);
	assign z = x ^~ y;
endmodule