FPGA/HDLBits
Dff8r
장영현
2023. 6. 13. 19:40
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Problem Statement
Create 8 D flip-flops with active high synchronous reset. All DFFs should be triggered by the positive edge of clk.
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if(reset)
q = 0;
else
q = d;
end
endmodule