Exams/ece241 2013 q7

Problem Statement

A JK flip-flop has the below truth table. Implement a JK flip-flop with only a D-type flip-flop and gates. Note: Qold is the output of the D flip-flop before the positive clock edge.

 

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always @(posedge clk)begin
        if(j == 0 && k == 0)
            Q <= Q;
        else if(j == 0 && k == 1)
            Q <= 0;
        else if(j == 1 && k == 0)
            Q <= 1;
        else if(j == 1 && k == 1)
            Q <= ~Q;
    end
endmodule