FPGA/HDLBits

Vector100r

장영현 2023. 6. 20. 00:36
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Problem Statement

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always @(*) begin
        for(i = 0; i < 100; i++) begin
            out[99-i] = in[i];
        end
    end

endmodule