FPGA/HDLBits

Count15

장영현 2023. 6. 20. 10:51
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Problem Statement

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    
    always @(posedge clk) begin
        if(reset)
            q = 0;
        else if(q == 4'hf)
            q = 0;
        else
            q = q + 1;
    end
endmodule