FPGA/HDLBits

Count10

장영현 2023. 6. 20. 11:18
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Problem Statement

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);

    always @(posedge clk) begin
        if(reset)
            q = 0;
        else begin
            q = q + 1;
            if(q == 4'ha)
            q = 0;
        end
    end
endmodule