FPGA/HDLBits

Count1to10

장영현 2023. 6. 20. 11:23
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Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    
    always @ (posedge clk) begin
        if(reset) 
            q = 4'h1;
        else begin
            q = q + 1;
            if(q == 4'hb)
                q = 4'h1;
        end
    end
endmodule