FPGA/HDLBits

Vectorgates

장영현 2023. 6. 9. 00:18
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Problem Statement

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

 

 

//성공 코드
module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise [2] = a[2] | b[2];
    assign out_or_bitwise [1] = a[1] | b[1];
    assign out_or_bitwise [0] = a[0] | b[0];
    
    assign out_or_logical = a || b;
    
    assign out_not [5:3] = ~b;
    assign out_not [2:0] = ~a;
endmodule

//실패 코드
module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise [2] = a[2] | b[2];
    assign out_or_bitwise [1] = a[1] | b[1];
    assign out_or_bitwise [0] = a[0] | b[0];
    
    assign out_or_logical = a | b;
    
    assign out_not[5] = !a[2];
    assign out_not[4] = !a[1];
    assign out_not[3] = !a[0];
    assign out_not[2] = !b[2];
    assign out_not[1] = !b[1];
    assign out_not[0] = !b[2];
endmodule
//out_or_bitwise = 비트연산자 | / out_or_logical = 논리연산자 || / out_not = 비트연산자 ~ 사용해야한다