Exams/m2014 q4j
2023. 6. 13. 18:50ㆍFPGA/HDLBits
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Problem Statement
Implement the following circuit:
("FA" is a full adder)
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum);
reg [2:0] cout;
reg cin;
FA U1(
.x(x[0]),
.y(y[0]),
.sum(sum[0]),
.cout(cout[0])
);
FA U2(
.x(x[1]),
.y(y[1]),
.cin(cout[0]),
.sum(sum[1]),
.cout(cout[1])
);
FA U3(
.x(x[2]),
.y(y[2]),
.cin(cout[1]),
.sum(sum[2]),
.cout(cout[2])
);
FA U4(
.x(x[3]),
.y(y[3]),
.cin(cout[2]),
.sum(sum[3]),
.cout(sum[4])
);
endmodule
module FA (
input x,y,cin,
output sum,cout
);
assign {cout,sum} = x + y + cin;
endmodule