See Lfsr5 for explanations. Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. module top_module( input clk, input reset, // Active-high synchronous reset to 32'h1 output [31:0] q ); always @(posedge clk) begin if(reset) q

A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A m..

Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented. You may want to instantiate or modify some one-digit decade counters. module top_module ( input clk, input reset, // Synchronous..

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable. areset: Resets shift register to zero. load: Loads shift register with data[3:0] instead of shifting. ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears). q: The contents of the shift register. If both the load and ena inputs are asserted (1), the load input has higher priority..

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input clock, input a, output p, output q ); always @(*) begin if(clock) p = a; end always @(negedge clock) begin q

See also: State transition logic for this FSM The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.) StateNext stateOutputin=0in=1 A A B 0 B C B 0 C A D 0 D C B 1 module top_module( i..