Dff8p
2023. 6. 13. 19:46ㆍFPGA/HDLBits
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Problem Statement
Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk.
//성공 코드
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @ (negedge clk) begin
if(reset)
q = 8'h34;
else
q = d;
end
endmodule
//실패 코드
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @ (negedge clk) begin
if(reset)
q = 0;
else
q = d;
end
endmodule
//The flip-flops must be reset to 0x34 rather than zero