Exams/ece241 2014 q4

Problem Statement

Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.

Build this circuit.

module top_module (
    input clk,
    input x,
    output z
	); 
    reg Q_1 = 1'b0;
    reg Q_2 = 1'b0;
    reg Q_3 = 1'b0;
    
    wire xor_gate;
    wire and_gate;
    wire or_gate;
    
    always @(posedge clk)begin
    	xor_gate = x ^ Q_1;
        Q_1 <= xor_gate;
    end
    
    always @(posedge clk)begin
        and_gate = x & (~Q_2);
        Q_2 <= and_gate;
    end
    
    always @(posedge clk)begin
        or_gate = x | (~Q_3);
        Q_3 <= or_gate;
    end
        
    assign z = ~(xor_gate | and_gate | or_gate);
endmodule

 

---

 

module top_module (
    input clk,
    input x,
    output z
	); 
    reg Q_1 = 1'b0;
    reg Q_2 = 1'b1;
    reg Q_3 = 1'b1;
    wire xor_gate;
    wire and_gate;
    wire or_gate;
    
    always @(posedge clk)begin
    	xor_gate <= x ^ Q_1;
        Q_1 <= xor_gate;
    end
    
    always @(posedge clk)begin
    	and_gate <= x & Q_2;
        Q_2 <= ~(and_gate);
    end
    
    always @(posedge clk)begin
    	or_gate <= x | Q_3;
        Q_3 <= ~(or_gate);
    end
        
    assign z = ~(xor_gate | and_gate | or_gate);
endmodule

 

non-blocking과 blocking의 차이로 오류 발생

Q_1, Q_2, Q_3는 다음클럭의 입력으로 넣어 줘야해서 non-blocking 해야 하고, xor_gate, and_gate, or_gate는 해당클럭에서 즉각적으로 출력해줘야 해서 blocking 해줘야 한다.