Sim/circuit9
2023. 6. 20. 20:31ㆍFPGA/HDLBits
728x90
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.
module top_module (
input clk,
input a,
output [3:0] q );
always @(posedge clk) begin
if(a)
q <= 3'o4;
else begin
q <= q + 1;
if(q == 3'o6)
q <= 3'o0;
end
end
endmodule
'FPGA > HDLBits' 카테고리의 다른 글
Always casez (0) | 2023.06.24 |
---|---|
Always case2 (0) | 2023.06.24 |
Sim/circuit7 (0) | 2023.06.20 |
Sim/circuit6 (0) | 2023.06.20 |
Sim/circuit5 (0) | 2023.06.20 |