Reduction

2023. 6. 24. 22:29FPGA/HDLBits

728x90

Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bit

module top_module (
    input [7:0] in,
    output parity); 

    assign parity = (^in == 1) ? 1 : 0 ;
endmodule

'FPGA > HDLBits' 카테고리의 다른 글

Bcdadd100  (0) 2023.06.26
Adder100i  (0) 2023.06.25
Conditional  (0) 2023.06.24
Always nolatches  (0) 2023.06.24
Always casez  (0) 2023.06.24