Vector0

2023. 6. 8. 23:38FPGA/HDLBits

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Problem Statement

Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc.

 

In a diagram, a tick mark with a number next to it indicates the width of the vector (or "bus"), rather than drawing a separate line for each bit in the vector.

 

//성공 코드
module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
	
    assign outv = vec;
    assign o2 = vec[2];
    assign o0 = vec[0];
    assign o1 = vec[1];
    
endmodule

//실패 코드
module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); // Module body starts after module declaration
	
    assign o0 = vec[0];
    assign o1 = vec[1];
    assign o2 = vec[2];
    
    assign outv = vec;
endmodule
//벡터를 밑에서 위로 선언하는 것은 안되고, 위에서 밑으로 내려가며 선언하면 가능

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