Wire (Exams/m2014 q4h)
2023. 6. 12. 09:15ㆍFPGA/HDLBits
728x90
Problem Statement
Implement the following circuit:
module top_module (
input in,
output out);
assign out = in;
endmodule'FPGA > HDLBits' 카테고리의 다른 글
| NOR (Exams/m2014 q4e) (0) | 2023.06.12 |
|---|---|
| GND (Exams/m2014 q4i) (0) | 2023.06.12 |
| Always case (0) | 2023.06.12 |
| Always if2 (0) | 2023.06.10 |
| Always if (0) | 2023.06.10 |