Exams/m2014 q4k

Implement the following circuit:

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output reg out);

    reg out1, out2, out3;
    
    always @(posedge clk) begin
        if(!resetn) begin
       	 	out1 <= 1'b0;
        	out2 <= 1'b0;
            out3 <= 1'b0;
            out <= 1'b0;
            end else begin 
            out1 <= in;
        	out2 <= out1;
            out3 <= out2;
            out <= out3;
        end
    end

endmodule

 

 

---

 

//실패 코드
module top_module (
    input clk,
    input resetn,   // synchronous reset 
    input in,
    output out
);
    wire [3:0] data;
    
    dff dff1(clk, resetn, in, data[0]);
    dff dff2(clk, resetn, data[0], data[1]);
    dff dff3(clk, resetn, data[1], data[2]);
    dff dff4(clk, resetn, data[2], data[3]);
    
    assign out = data[3];
    
endmodule

module dff(
    input clk,
    input reset,
    input in,
    output reg out
);

    always @(posedge clk or negedge reset) begin
        if (!reset)
            out <= 1'b1;
        else 
            out <= in;
    end

endmodule