Mt2015 lfsr

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Mt2015 muxdff - HDLBits

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.

 

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
	
    
    mt2015(KEY[0], KEY[1], SW[0], LEDR[2], LEDR[0]);
    mt2015(KEY[0], KEY[1], SW[1], LEDR[0], LEDR[1]);
    
    wire xor_mux;
    assign xor_mux = LEDR[1] ^ LEDR[2];
    
    mt2015(KEY[0], KEY[1], SW[2], xor_mux, LEDR[2]);
   
endmodule

module mt2015(
	input clk,
    input L,
    input in1,
    input in2,
    output Q
);
     wire [2:0] mux_out;
    
    assign mux_out = L ? in1 : in2; 
    
    always @(posedge clk)begin
        Q <= mux_out;        
    end
endmodule