Module fadd

2023. 6. 10. 18:43FPGA/HDLBits

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Problem Statement

Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

In summary, there are three modules in this design:

  • top_module — Your top-level module that contains two of...
  • add16, provided — A 16-bit adder module that is composed of 16 of...
  • add1 — A 1-bit full adder module.


If your submission is missing a module add1, you will get an error message that says Error (12006): Node instance "user_fadd[0].a1" instantiates undefined entity "add1".

 

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] sum1, sum2;
    wire cout1, cout2;

    add16 instance1 (a[15:0], b[15:0], 1'b0, sum1, cout1);
    add16 instance2 (a[31:16], b[31:16], cout1, sum2, cout2);
	
	assign sum = {sum2, sum1};
    
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
 
// Full adder module here

    assign sum = a^b^cin;
    assign cout = a&b | a&cin | b&cin;
    
endmodule

 


 

 

전가산기 회로도

전가산기 회로도를 이용하여 부울대수를 적은 후, 해당 식을 assign 을 이용하여 S와 Cout을 생성하면 된다.

  1. assign sum = a^b^cin;
  2. assign cout = a&b | a&cin | b&cin;

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