Mux2to1

Problem Statement

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
	
    reg out_data;
    
    always @(*) begin
        case (sel)
            1'b0 : out_data = a;
            1'b1 : out_data = b;
        endcase
    end
    
    assign out = out_data;
endmodule