FND&디코더
2023. 6. 15. 19:08ㆍ[Harman] 세미콘(semiconductor) 아카데미-반도체설계/Verilog를 이용한 RTL 시스템 반도체 설계
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우리가 사용하는 보드(BASYS3)의 FND는 4개 존재
이 FND를 개별로 사용하려면 counter를 이용하여 각각 다른 시간의 값을 FND에 부여해야 개별로 사용가능
Clock Div -> Counter -> MUX -> Decoder & FND
- EXAMPLE 1
`timescale 1ns / 1ps
module FNDSEL(
input clk,
input [1:0] fndselin,
output reg [3:0] out
);
always @ (posedge clk) begin
case (fndselin)
2'b00 : out = 4'b1110;
2'b01 : out = 4'b1101;
2'b10 : out = 4'b1011;
2'b11 : out = 4'b0111;
endcase
end
endmodule`timescale 1ns / 1ps
module FND_Decoder_4x8(
input clk,
input [3:0] fndin,
output reg [7:0] out
);
always @(posedge clk) begin
case(fndin)
4'b0000 : out = 8'b01000000; //0
4'b0001 : out = 8'b01111001; //1
4'b0010 : out = 8'b00100100; //2
4'b0011 : out = 8'b00110000; //3
4'b0100 : out = 8'b00011001; //4
4'b0101 : out = 8'b00010010; //5
4'b0110 : out = 8'b000000010; //6
4'b0111 : out = 8'b01011000; //7
4'b1000 : out = 8'b000000000; //8
4'b1001 : out = 8'b000010000; //9
4'b1010 : out = 8'b00100000; //10
4'b1011 : out = 8'b00000011; //11
4'b1100 : out = 8'b00100111; //12
4'b1101 : out = 8'b00100001; //13
4'b1110 : out = 8'b00000100; //14
4'b1111 : out = 8'b00001110; //15
endcase
end
endmodule`timescale 1ns / 1ps
module top_fndcontrol(
input clk,
input [1:0] fndselin,
input [3:0] fndin,
output [3:0] out_mux,
output [7:0] out_dec
);
FNDSEL mux(.clk(clk), .fndselin(fndselin), .out(out_mux));
FND_Decoder_4x8 dec(.clk(clk), .fndin(fndin), .out(out_dec));
endmodule
//xdc 파일
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {fndin[0]}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {fndin[1]}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {fndin[2]}]
set_property -dict { PACKAGE_PIN w17 IOSTANDARD LVCMOS33 } [get_ports {fndin[3]}]
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports {fndselin[0]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {fndselin[1]}]
##7 Segment Display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[0]}]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {out_dec[1]}]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {out_dec[2]}]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {out_dec[3]}]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {out_dec[4]}]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {out_dec[5]}]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[6]}]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[7]}]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {out_mux[0]}]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[1]}]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[2]}]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[3]}]
- EXAMPLE 2-1
`timescale 1ns / 1ps
module clockDivider(
input clk,
input reset_n,
output reg clk100Hz
);
reg [25:0] cnt = 0;
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
cnt <= 26'b0;
clk100Hz <= 1'b0;
end
else if(cnt == (26'd50000 - 1)) begin
cnt = 26'd0;
clk100Hz <= ~clk100Hz;
end else
cnt = cnt +1'b1;
end
endmodule`timescale 1ns / 1ps
module COUNTER(
input reset_n,
input clk100Hz,
output reg [1:0] count
);
always @(posedge clk100Hz or negedge reset_n) begin
if(!reset_n)
count <= 2'b0;
else
count <= count + 1'b1;
end
endmodule`timescale 1ns / 1ps
module FNDSEL(
input clk,
input [1:0] fndselin,
output reg [3:0] out
);
always @ (posedge clk) begin
case (fndselin)
2'b00 : out = 4'b1110;
2'b01 : out = 4'b1101;
2'b10 : out = 4'b1011;
2'b11 : out = 4'b0111;
endcase
end
endmodule`timescale 1ns / 1ps
module FND_Decoder_4x8(
input clk,
input [3:0] fndin,
output reg [7:0] out
);
always @(posedge clk) begin
case(fndin)
4'b0000 : out = 8'b01000000; //0
4'b0001 : out = 8'b01111001; //1
4'b0010 : out = 8'b00100100; //2
4'b0011 : out = 8'b00110000; //3
4'b0100 : out = 8'b00011001; //4
4'b0101 : out = 8'b00010010; //5
4'b0110 : out = 8'b000000010; //6
4'b0111 : out = 8'b01011000; //7
4'b1000 : out = 8'b000000000; //8
4'b1001 : out = 8'b000010000; //9
4'b1010 : out = 8'b00100000; //10
4'b1011 : out = 8'b00000011; //11
4'b1100 : out = 8'b00100111; //12
4'b1101 : out = 8'b00100001; //13
4'b1110 : out = 8'b00000100; //14
4'b1111 : out = 8'b00001110; //15
endcase
end
endmodule`timescale 1ns / 1ps
module top_fndcontrol(
input clk,
input reset_n,
input [1:0] fndselin,
input [3:0] fndin,
output [3:0] out_mux,
output [7:0] out_dec
);
wire w_clkout;
wire [1:0] w_counter;
clockDivider clock_d (.clk(clk), .reset_n(reset_n), .clk100Hz(w_clkout));
COUNTER cnt(.reset_n(reset_n), .clk100Hz(w_clkout), .count(w_counter));
FNDSEL mux (.clk(clk), .fndselin(w_counter), .out(out_mux));
FND_Decoder_4x8 dec (.clk(clk), .fndin(fndin), .out(out_dec));
endmodule
//xdc 파일
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {fndin[0]}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {fndin[1]}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {fndin[2]}]
set_property -dict { PACKAGE_PIN w17 IOSTANDARD LVCMOS33 } [get_ports {fndin[3]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {reset_n}]
##7 Segment Display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[0]}]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {out_dec[1]}]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {out_dec[2]}]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {out_dec[3]}]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {out_dec[4]}]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {out_dec[5]}]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[6]}]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {out_dec[7]}]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {out_mux[0]}]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[1]}]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[2]}]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[3]}]
- EXAMPLE 2-2
`timescale 1ns / 1ps
module clockDivider(
input clk,
input reset_n,
output reg clk100Hz
);
reg [25:0] cnt = 0;
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
cnt <= 26'b0;
clk100Hz <= 1'b0;
end
else if(cnt == (26'd50000 - 1)) begin
cnt = 26'd0;
clk100Hz <= ~clk100Hz;
end else
cnt = cnt +1'b1;
end
endmodule`timescale 1ns / 1ps
module COUNTER(
input reset_n,
input clk100Hz,
output reg [1:0] count
);
always @(posedge clk100Hz or negedge reset_n) begin
if(!reset_n)
count <= 2'b0;
else
count <= count + 1'b1;
end
endmodule`timescale 1ns / 1ps
module FNDSEL(
input clk,
input [1:0] fndselin,
output reg [3:0] out
);
always @ (posedge clk) begin
case (fndselin)
2'b00 : out = 4'b1110;
2'b01 : out = 4'b1101;
2'b10 : out = 4'b1011;
2'b11 : out = 4'b0111;
endcase
end
endmodule`timescale 1ns / 1ps
module dataMUX(
input clk,
input [3:0] ina,
input [3:0] inb,
input [3:0] inc,
input [3:0] ind,
input [1:0] w_counter,
output reg [3:0] out
);
always @(posedge clk) begin
case(w_counter)
2'b00 : out = ina;
2'b01 : out = inb;
2'b10 : out = inc;
2'b11 : out = ind;
endcase
end
endmodule`timescale 1ns / 1ps
module FND_Decoder_4x8(
input clk,
input [3:0] fndin,
output reg [7:0] out
);
always @(posedge clk) begin
case(fndin)
4'b0000 : out = 8'b01000000; //0
4'b0001 : out = 8'b01111001; //1
4'b0010 : out = 8'b00100100; //2
4'b0011 : out = 8'b00110000; //3
4'b0100 : out = 8'b00011001; //4
4'b0101 : out = 8'b00010010; //5
4'b0110 : out = 8'b000000010; //6
4'b0111 : out = 8'b01011000; //7
4'b1000 : out = 8'b000000000; //8
4'b1001 : out = 8'b000010000; //9
4'b1010 : out = 8'b00100000; //10
4'b1011 : out = 8'b00000011; //11
4'b1100 : out = 8'b00100111; //12
4'b1101 : out = 8'b00100001; //13
4'b1110 : out = 8'b00000100; //14
4'b1111 : out = 8'b00001110; //15
default : out = 8'b11111111;
endcase
end
endmodule`timescale 1ns / 1ps
module top_fndcontrol(
input clk,
input reset_n,
input [3:0] ina,
input [3:0] inb,
input [3:0] inc,
input [3:0] ind,
output [3:0] out_mux,
output [7:0] FND
);
wire w_clkout;
wire [1:0] w_counter;
wire [3:0] fndin;
clockDivider clock_d (.clk(clk), .reset_n(reset_n), .clk100Hz(w_clkout));
COUNTER cnt(.reset_n(reset_n), .clk100Hz(w_clkout), .count(w_counter));
FNDSEL mux_1 (.clk(clk), .fndselin(w_counter), .out(out_mux));
dataMUX mux_2(.clk(clk), .ina(ina), .inb(inb), .inc(inc), .ind(ind), .w_counter(w_counter), .out(fndin));
FND_Decoder_4x8 dec (.clk(clk), .fndin(fndin), .out(FND));
endmodule
## Clock signal
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {ina[0]}]
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports {ina[1]}]
set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports {ina[2]}]
set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports {ina[3]}]
set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports {inb[0]}]
set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports {inb[1]}]
set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports {inb[2]}]
set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports {inb[3]}]
set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports {inc[0]}]
set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports {inc[1]}]
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports {inc[2]}]
set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports {inc[3]}]
set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports {reset_n}]
##7 Segment Display
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports {FND[0]}]
set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports {FND[1]}]
set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports {FND[2]}]
set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports {FND[3]}]
set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports {FND[4]}]
set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports {FND[5]}]
set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports {FND[6]}]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports {FND[7]}]
set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports {out_mux[0]}]
set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[1]}]
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[2]}]
set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports {out_mux[3]}]
##Buttons
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports {ind[0]}]
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports {ind[1]}]
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports {ind[2]}]
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports {ind[3]}]
'[Harman] 세미콘(semiconductor) 아카데미-반도체설계 > Verilog를 이용한 RTL 시스템 반도체 설계' 카테고리의 다른 글
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