리플 가산기

`timescale 1ns / 1ps

module RippleCarryAdder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum,
    output [3:0] c
);
    HalfAdder HA1(a[0], b[0], sum[0], c[0]);
    FullAdder FA2(a[1], b[1], c[0], sum[1], c[1]);
    FullAdder FA3(a[2], b[2], c[1], sum[2], c[2]);
    FullAdder FA4(a[3], b[3], c[2], sum[3], c[3]);
endmodule

module HalfAdder(
    input a,
    input b,
    output sum,
    output carry
    );
    
    assign sum = a ^ b;
    assign carry = a & b;
    
endmodule

module FullAdder(
  input a,
  input b,
  input cin,
  output sum,
  output cout
);
  wire s1, c1, c2;
  HalfAdder HA1(.a(a), .b(b), .sum(s1), .carry(c1));
  HalfAdder HA2(.a(s1), .b(cin), .sum(sum), .carry(c2));
  assign cout = c1 | c2;
endmodule​

`timescale 1ns / 1ps

module clockDivider(
    input clk,
    input reset_n,   
    output reg clk100Hz
    );
    
    reg [25:0] cnt = 0;
    
    always @(posedge clk or negedge reset_n) begin
        if(!reset_n) begin 
            cnt <= 26'b0;
            clk100Hz <= 1'b0; 
        end
        else if(cnt == (26'd50000 - 1)) begin
             cnt <= 26'd0;
             clk100Hz <= ~clk100Hz;
        end else
             cnt <= cnt +1'b1;    
    end
    
endmodule

`timescale 1ns / 1ps

module COUNTER(
    input reset_n,
    input clk100Hz,
    output reg [1:0] count
    );
    
    always @(posedge clk100Hz or negedge reset_n) begin
        if(!reset_n) 
            count <= 2'b0;
        else
            count <= count + 1'b1;    
    end
    
endmodule

`timescale 1ns / 1ps

module FNDSEL(
    input clk,
    input [1:0] fndselin,
    output reg [3:0] out
    );
    
    always @ (posedge clk) begin
        case (fndselin)
        2'b00 : out = 4'b1110;
        2'b01 : out = 4'b1101;
        2'b10 : out = 4'b1011;
        2'b11 : out = 4'b0111;
        endcase
    end
   
endmodule

`timescale 1ns / 1ps

module dataMUX(
    input clk,
    input [3:0] a,
    input [3:0] b,
    input [3:0] sum,
    input [3:0] carry,
    input [1:0] w_counter, 
    output reg [3:0] out
    );
    
    always @(posedge clk) begin
    
        case(w_counter)
        2'b00 : out = a;
        2'b01 : out = b;
        2'b10 : out = sum;
        2'b11 : out = carry;
        endcase
    end
endmodule

`timescale 1ns / 1ps

module FND_Decoder_4x8(
    input clk,
    input [3:0] fndin,
    output reg [7:0] out
    ); 

    always @(posedge clk) begin
        case(fndin)
            4'b0000 : out = 8'b01000000; //0
			4'b0001 : out = 8'b01111001; //1
			4'b0010 : out = 8'b00100100; //2
			4'b0011 : out = 8'b00110000; //3
			4'b0100 : out = 8'b00011001; //4
			4'b0101 : out = 8'b00010010; //5
			4'b0110 : out = 8'b000000010; //6
			4'b0111 : out = 8'b01011000; //7
			4'b1000 : out = 8'b000000000; //8
			4'b1001 : out = 8'b000010000; //9
			4'b1010 : out = 8'b00100000; //10
			4'b1011 : out = 8'b00000011; //11
			4'b1100 : out = 8'b00100111; //12
			4'b1101 : out = 8'b00100001; //13
			4'b1110 : out = 8'b00000100; //14
			4'b1111 : out = 8'b00001110; //15
			default : out = 8'b11111111;
		endcase
    end
endmodule

`timescale 1ns / 1ps

module top_fndcontrol(
    input clk,
    input reset_n,
    input [3:0] a,
    input [3:0] b,
    output [3:0] out,
    output [7:0] FND
    );
    wire clk100Hz;
    wire [3:0] adder_sum;
    wire [3:0] datamux_out;
    wire [1:0] w_count;
    wire [3:0] c;
    
    clockDivider clock (.clk(clk), .reset_n(reset_n), .clk100Hz(clk100Hz));
    
    COUNTER coun(.reset_n(reset_n), .clk100Hz(clk100Hz), .count(w_count));
    
    FNDSEL fnd1(.clk(clk), .fndselin(w_count), .out(out));
    
    RippleCarryAdder carrya(.a(a), .b(b), .sum(adder_sum), .c(c));
    
    dataMUX mux (.clk(clk), .a(a), .b(b), .sum(adder_sum), .carry({3'b0,c[3]}), .w_counter(w_count), .out(datamux_out));
    
    FND_Decoder_4x8 fnd2(.clk(clk), .fndin(datamux_out), .out(FND));
    
endmodule

 

## Clock signal
set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {a[0]}]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {a[1]}]
set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports {a[2]}]
set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports {a[3]}]
set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports {b[0]}]
set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports {b[1]}]
set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports {b[2]}]
set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports {b[3]}]
set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {reset_n}]

##7 Segment Display
set_property -dict { PACKAGE_PIN W7   IOSTANDARD LVCMOS33 } [get_ports {FND[0]}]
set_property -dict { PACKAGE_PIN W6   IOSTANDARD LVCMOS33 } [get_ports {FND[1]}]
set_property -dict { PACKAGE_PIN U8   IOSTANDARD LVCMOS33 } [get_ports {FND[2]}]
set_property -dict { PACKAGE_PIN V8   IOSTANDARD LVCMOS33 } [get_ports {FND[3]}]
set_property -dict { PACKAGE_PIN U5   IOSTANDARD LVCMOS33 } [get_ports {FND[4]}]
set_property -dict { PACKAGE_PIN V5   IOSTANDARD LVCMOS33 } [get_ports {FND[5]}]
set_property -dict { PACKAGE_PIN U7   IOSTANDARD LVCMOS33 } [get_ports {FND[6]}]
set_property -dict { PACKAGE_PIN V7   IOSTANDARD LVCMOS33 } [get_ports {FND[7]}]

set_property -dict { PACKAGE_PIN U2   IOSTANDARD LVCMOS33 } [get_ports {out[0]}]
set_property -dict { PACKAGE_PIN U4   IOSTANDARD LVCMOS33 } [get_ports {out[1]}]
set_property -dict { PACKAGE_PIN V4   IOSTANDARD LVCMOS33 } [get_ports {out[2]}]
set_property -dict { PACKAGE_PIN W4   IOSTANDARD LVCMOS33 } [get_ports {out[3]}]