Countbcd

2023. 6. 28. 15:47FPGA/HDLBits

728x90

Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.

You may want to instantiate or modify some one-digit decade counters.

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);

    assign ena[1] = (q[3:0] == 4'd9) ? 1'b1 : 1'b0;
    assign ena[2] = (q[3:0] == 4'd9 && q[7:4] == 4'd9) ? 1'b1 : 1'b0;
    assign ena[3] = (q[3:0] == 4'd9 && q[7:4] == 4'd9 && q[11:8] == 4'd9) ? 1'b1 : 1'b0;
    
    BCD BCD1(.clk(clk), .reset(reset), .ena(1'b1), .q(q[3:0]));
    BCD BCD2(.clk(clk), .reset(reset), .ena(ena[1]), .q(q[7:4]));
    BCD BCD3(.clk(clk), .reset(reset), .ena(ena[2]), .q(q[11:8]));
    BCD BCD4(.clk(clk), .reset(reset), .ena(ena[3]), .q(q[15:12]));
endmodule

module BCD (
	input clk,
    input reset,
    input ena,
    output reg [3:0] q
);
    always @(posedge clk)begin
        if(reset)
            q <= 1'b0;
        else if(ena) begin
            if(q == 4'd9) begin
                q <= 4'd0;
            end else
                q <= q + 1'b1;
        end
    end
endmodule

 

 

'FPGA > HDLBits' 카테고리의 다른 글

Lfsr32  (0) 2023.06.28
Exams/2014 q4b  (0) 2023.06.28
Shift4  (0) 2023.06.28
Sim/circuit8  (0) 2023.06.28
Fsm3s  (0) 2023.06.28