FPGA(150)
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Always case2
A priority encoder is a combinational circuit that, when given an input bit vector, outputs the position of the first 1 bit in the vector. For example, a 8-bit priority encoder given the input 8'b10010000 would output 3'd4, because bit[4] is first bit that is high. Build a 4-bit priority encoder. For this problem, if none of the input bits are high (i.e., input is zero), output zero. Note that a..
2023.06.24 -
Sim/circuit9
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input clk, input a, output [3:0] q ); always @(posedge clk) begin if(a) q
2023.06.20 -
Sim/circuit7
This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input clk, input a, output q ); always @(posedge clk)begin q
2023.06.20 -
Sim/circuit6
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input [2:0] a, output [15:0] q ); always @ (*) case (a) 3'o0 : q = 16'h1232; 3'o1 : q = 16'haee0; 3'o2 : q = 16'h27d4; 3'o3 : q = 16'h5a0e; 3'o4 : q = 16'h2066; 3'o5 : q = 16'h64ce; 3'o6 : q = 16'hc526; 3'o7 : q = 16'h2f19; endcase endmodule
2023.06.20 -
Sim/circuit5
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it. module top_module ( input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [3:0] e, output [3:0] q ); always @ (*) case (c) 4'h0 : q = b; 4'h1 : q = e; 4'h2 : q = a; 4'h3 : q = d; default q = 4'hf; endcase endmodule
2023.06.20 -
Sim/circuit4
This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it. b나 c가 1일때 q가 high인 상태 module top_module ( input a, input b, input c, input d, output q );// assign q = b | c; // Fix me endmodule
2023.06.20